Integrated memory circuits use sense amplifiers to read a memory state from a selected memory cell. A detailed operation of the sense amplifier is described, for example, in U.S. Pat. No. 4,397,003 to Wilson et al. As shown in the Wilson patent, each sense amplifier receives a pair of bit lines. The bit lines are precharged to a given potential. Once precharged, the selected memory cell is connected to one of the bit lines. The sense amplifier senses the voltage differential on the two bit lines and generates outputs on the bit lines corresponding to the memory state of the selected memory cell.
Because sense amplifiers occupy relatively large layout space, each sense amplifier is typically shared between multiple bit line pairs. For example, the memory array in an integrated memory circuit is divided into two sections and the bit line pair from each section are connected to the same sense amplifier. To isolate one bit line pair from the sense amplifier when reading from the other pair, an isolation transistor is positioned between the sense amplifier and each bit line. Thus, to isolate one bit line pair the corresponding isolation transistors turn off to disconnect those bit lines from the sense amplifier. For the other bit line pair to be accessed, on the other hand, the corresponding isolation transistors turn on to connect those bit lines to the sense amplifier.
When the selected memory cell is being accessed, the voltage differential of the bit line pair is in the relatively low range of 100 millivolts to 200 millivolts. In order to sense such low voltage differentials, it is important to be able to pass the full voltage from the bit line pair to the sense amplifier without a significant voltage drop across the isolation transistors. However, voltage drops across the isolation transistors can be avoided only by driving the gates of the isolation transistors to a higher voltage than the supply voltage. The higher voltage should be greater than the sum of the supply voltage and the threshold voltage of the isolation transistors. For a supply voltage Vcc of 3 volts, the threshold voltage of the isolation transistor may be approximately 1.2 volts. Accordingly, the gate voltage of the isolation transistor should be driven to at least 4.2 volts. Typically, the required higher voltage is generated from a charge pump. The charge pump receives the supply voltage Vcc and pumps it up to a pumped voltage Vccp. A driver circuit receives the pumped voltage and drives the gates of the isolation transistors to the pumped voltage Vccp.
FIG. 1 shows a block diagram of a prior art driver circuit connected to the isolation transistors. A sense amplifier 12 is connected to a bit line pair 14-16 of memory array section A and a bit line pair 18-20 of memory array section B. Isolation transistors 22-24 are connected to the bit line pair 18-20 and isolation transistors 26-28 are connected to the bit line pair 18-20. The gates of the transistors 22-24 are connected to a first output 6 of the driver circuit 10. The gates of the transistors 26-28 are connected to a second output 8. The driver circuit receives a pumped voltage Vccp generated from a charge pump (not shown). In operation, a row decoder (not shown) selectively addresses one row in array section A or array section B. A column decoder (not shown) selectively addresses one bit line. Through the addressed row line and bit line, one memory access transistor is coupled to the corresponding sense amplifier. When memory array section A is being accessed, the driver circuit 10 couples the gates of the isolation transistors 22-24 to the pumped voltage. Simultaneously, the driver circuit 10 drives the gates of the isolation transistors 18-20 to ground in order to isolate the bit line pair 18-20 from the sense amplifier 12.
One disadvantage of the driver circuit 10 is that because charge pumps are generally inefficient, raising the gate voltage from ground to the pumped voltage requires a large amount of current.
Thus, it would be desirable to provide a more efficient driver circuit to drive the gate voltage to the pumped voltage.